IES5501 bus buffer / repeater
Extend and expand your I2C, 2-Wire, SMBus, PMBus, IPMI or AccessBus Using analog design principles, the IES5501 is a true bi-directional bus buffer for use in 2- wire bus systems such as I²C, SMBus, PMBus & IPMB etc*. The function of the bus buffer is to extend the bus load limit by buffering the Clock (SCL) and Data (SDA) lines. The IES5501 simplifies the design process in a 2-wire bus system; we have put the work into the chip to make your job easy. A dedicated bus buffer website has been developed to assist the 2-wire bus designer by providing detailed product specifications, application notes, FAQ and "Ask the Expert" more information at www.bus-buffer.com
features
Dual bi-directional unity gain buffer Fully I2C compliant & supports a wide range of 2-wire standards Doesn’t impose additional restrictions on logic levels Very low input to output offset voltages Multiple bus buffers allowed in cascade, multi-drop or “daisy chain” fashion Compatible with all other classes of 2-wire bus buffer Wide range of allowed bus voltages (1.8V to 15V)	Level shifting between bus voltages (1.8V to 15V) Superior response times Plugs in to live backplanes Chip enable allows bus disconnection No minimum bus capacitance requirement Low current stand-by mode when not enabled Application/removal of power to IC will not interfere with other bus activity Available in SO-8 and MSOP-8
applications
Telecommunications Systems (inc. ATCA) Radial IPMB architectures Power Management System Backplane Management / Interconnect Desktop and Portable Computers (inc. RAID) Compact PCIRExpress 2-Wire Bus Switch/Multiplexing Applications	2-Wire Bus Switch/Multiplexing Applications Automotive Accessories (up to 15V) Building Automation TV / Projector / Monitor interconnection Game Consoles / Boxes TV / Projector / Monitor interconnection Game Consoles / Boxes Gaming Machine Networks

The IES5501 bus buffer (Fig 1) is compatible for extending I2C, SMBusTM, PMbusTM and other similar 2-wire bus systems where optimum performance is required. They feature very low input to output offset voltages, allowing buffer cascading and increasing system reliability.

The buffer extends the bus load limit by buffering both the Clock (SCL) and Data (SDA) lines. It supports up to 400 pF loads on each side of the buffer at 400kHz. Higher capacitance is supported at lower speeds, and lower capacitance at higher speeds up to 1MHz. The unique operation of the IES5501 provides one of the fastest response times of such bi-directional buffers, ensuring any glitches (common to other buffers) are kept well within the 50 ns I2C specification.

The IES5501 significantly increase system noise margins on the intelligent platform management bus (IPMB) and are excellent for implementing cost effective IPMB architectures.

The wide allowable voltage range expands their potential in ATCA and CompactPCI power management systems, backplane management systems and for bus voltage level translation (1.8V to 15V). Figure 1 IES5501 Block Diagram

I²C^TM is a trademark of Philips Semiconductors Corporation
SMBus^TM and PMBus^TM are trademarks of System Management Interface Forum (SMIF) Inc
ATCA^TM PICMG^R CompactPCI^RExpress are Registered trademarks of PCI Industrial Computers Manufacturers Group